Research & Development
As a complement to the production of standard packages EEMS can fully develop or co-develop with customers specific package solutions, particularly in the areas of multichip MCPs, POPs PIPs and SIPs
Starting from the analsyis of the requirements our R&D cover all cycle from concept through the definition of the structure, of parts and of process, the simulations and the executing of design and prototyping.
Volume feasibility analysis, productive samples and lab qualification are then preparating the volume production start phase.
Solsonica
EEMS’ development team plays a key role within the company, both in terms of design and marketing of the products. EEMS’ R&D, in addition to continuously developing new packages and assembly techniques, modifies the packages in use, adapting them to each client's need.
Research & Development activities
Key enabling technologies
- 200 & 300mm wafer full processing capabilities
- Back-grinding as low as 90µm on both 200 & 300mm wafers
- DBG (Dicing Before Grinding) in addition to GBD (Grinding Before Dicing) capabilities
- Plasma etching stress relief
- Die attach technologies
- Non-conductive liquid, with fillers
- DAF: Die Attach Film
- Lead-on-Chip: tape and B-Stage technologies
- Wire bonding technologies
- Small pitches, 60 µm, and small pad openings, 45µm
- Several kind of loops: forward, low, reverse, cascade, long wires
- Thinner substrates: down to 80-100 µm
- Environmentally friendly versions: full green, ROHS compliant
- Compliance to industry standards: JEDEC, MMCA, SDA